1. Field of the Invention
The present invention is related to dual gate devices, capable of addressing individual points along the width of the device. In particular the present invention relates to high density multibit memory cells.
2. Description of the Related Technology
The majority of the current electronic appliances require non-volatile memories, capable of preserving stored information when the power supply is switched off. One of the most versatile classes of such non-volatile memories are flash memories, in which a single cell can be addressed and data stored upon, while a large number of cells can be electrically erased at the same time. Flash memories are widely used e.g. to store the basic input-output system (BIOS) of personal computers, the software and personal data of cellular phones, identification codes in smart cards and many other applications. Flash memories allow software updates, change of passwords and codes, and reconfiguration of the system in the field. They can be designed and optimized to create high-density data storage memories that can e.g. successfully substitute hard disks for specific applications, having lower power consumption and weight, shorter access times, and far better robustness. A flash memory cell typically comprises a charge storage layer, in which a bit in the form of a dedicated amount of charge can be stored and whereby this charge influences the current flow in a channel region under control of this charge storage layer, a program gate to bias the memory cell e.g. such that this charge is transported into the charge storage layer during programming and out of the charge storage layer during erasing, and a control gate to assist, during operation, in selecting the desired memory cell from a matrix of memory cells. The charge storage layer can be of a conductive material, such as polysilicon, surrounded by dielectric layers or can be of a non-conductive material such as nitride, e.g. silicon-nitride.
Manufacturers of flash memories are forced to increase the performance of the memories in terms of, e.g., density, speed, power consumption, and to decrease process cost. To increase the data density of the flash memory cell, i.e. the number of bits that can be stored within a given area, two approaches are currently used. One approach is to scale down the geometry of a single bit memory cell in accordance with the International Roadmap for Semiconductors (ITRS). This roadmap forecasts the use of 90 nm technology in 2004 and 65 nm technology in 2007. Although addressing the individual bit in case of single bit memory cells is easier, such continuous scaling however requires a combined effort of the whole semiconductor industry including semiconductor device manufacturers, equipment and material suppliers. When going from one technology node to another the semiconductor device manufacturer will be obliged to acquire a new generation of semiconductor technology and to convert this technology from a research object into a production worthy tool, which can be a very time and resource consuming process. Another approach to increase the density of the flash memory is to store more than one bit within the charge storage layer of the memory cell. One can distinguish multi-state or multi-level memory cells in which a different amount of charge can be stored at the same location within the charge storage layer, each amount corresponding to a different value of the bit. In this respect the absence of charge corresponds to a “0” value of bit, a first amount of charge to a “1” value, a second, higher, amount of charge to a “2” value, etcetera. U.S. Pat. No. 6,320,786 “Method of controlling a multi-state NROM” illustrates such a multi-level memory cell in the form of a multi-state NROM device. Such a multi-state or multi-level approach would require a precise control over the amount of electrical charge trapped within the charge storage layer so as to obtain clearly distinct data values. Although the number of bits stored in a memory cell is, in first instance, not coupled to the minimal feature size of the technology used, in practice this multilevel approach is limited to a few bits per cell. An alternative approach is to store multiple, substantially identical, amounts of charge at different locations along the channel length within the same charge storage layer. With each of these locations a bit is associated having either a “0” value, i.e. no charge stored at this location, or a “1” value, i.e. a dedicated amount of charge stored at this location. U.S. Pat. No. 6,580,120 “Two bit non-volatile electrically erasable and programmable memory structure, a process for producing the memory structure and methods for programming, reading and erasing the memory structure” discloses a dual bit flash EEPROM, in which a single FET functions as a memory cell. The disclosed flash cell uses a Field Effect Transistor (FET) in which silicon nitride is used as gate dielectric to store charge therein, while the polysilicon gate is used as program gate. By appropriately reversing the applied voltages, a bit can be stored at either the source or the drain side of the FET. Each bit of the two bits within the memory cell can have a “0” or “1” value depending on whether or not charge is stored at the corresponding location. Although this approach offers a dense memory structure by forming adjacent polygates, this approach does not solve the scaling problem completely, as this multibit approach only allows storing two bits under each gate electrode.